Tutorials and Invited

Monday, September 25th



Simulation of Packaging under Harsh Environment Conditions

(Temperature, Pressure, Corrosion and Radiation)

Kirsten Weide-Zaage, RESRI Group, Institute of Microelectronic Systems (IMS),

Leibniz Universität Hannover, 30167 Hannover



An important role of microelectronic packages is the protection of the chip against environmental influences like moisture, pollutants and other chemical active species. If the chip is exposed by these influences for instance corrosion is resulting. Furthermore due to high temperature load and pressure or vibrations the reliability of the package is influenced by thermo-mechanical stress. The unavoidable presence of particle radiation on ground and in the atmosphere leads to unwanted failures in the electronic devices, partly affected by the package material and solder. All these harsh conditions have to be served more and more in the frame of automotive, medical and avionic applications. For space application all of these parameters are important as well.

Due to this, an essential aspect of the package design is the careful combination of materials to avoid mechanical stress and to improve the thermal-electrical and mechanical behavior as well as the corrosion resistance and radiation hardness of the package.

Simulation analysis can, using the appropriate software, depending on the material properties, the package geometry as well as the boundaries give a fast and reliable solution to investigate the influence of mechanical stress as well as the thermal, electrical and mechanical behavior of the package.



Review of the impact of microstructure of lead-free solder joints on assessment of fatigue lives of the solder joints by simulations and thermal cycling tests

Per-Erik Tegehall, Swerea IVF, Sweden



Lead-free solder joints based on Sn, Ag and Cu (SAC solders) have quite different microstructure compared to SnPb solder joints. A large fraction of solder joints to area array components consist of highly anisotropic single-grained solder joints. The orientation of the grains is basically random and has a large impact on the stress levels in the solder joints which will be unique for each solder joint. It will also have a large impact on the stress levels that the laminates beneath solder lands will be exposed to, which may cause cracking in the laminate under some solder joints. Such cracks formed in the PCB laminate will decrease the stress on the solder joint resulting in longer fatigue life. Therefore, due to this, a too accelerated thermal cycling test may result in an overestimation of the fatigue life in milder field conditions.

Another difference between SAC solders and SnPb solder is that the former have a high degree of precipitation hardening and solid solution hardening. This is important since especially a high level of precipitation hardening may prevent a recrystallisation of the solder which is often necessary before cracks can form in the solder joints. The degree of precipitation hardening may be affected by a number of parameters of which the most important are solder composition, solder volume and cooling rate after soldering. The degree of precipitation hardening will decrease with time. The higher the temperature, the faster decrease of the precipitation hardening. High strain will also cause faster decrease of the precipitation hardening. As a consequence, due to the impact of high temperature and high strain, a too accelerated test may lead to an underestimation of the fatigue life in milder field conditions.

This paper will discuss how to design adequate thermal cycling tests for assessing the fatigue life of SAC solder joints. It will also discuss how the large fractions of highly anisotropic single-grained solder joints when soldering using SAC solders will affect simulation of the fatigue lives of the solder joints.


Tuesday, September 26th



Aerospace trends are moving fast towards no more custom ICs to high reliability automotive solutions

R. Enrici Vaion(a), M. Medda(a), A. Pintus(a), A. Mancaleoni(a), G. Mura(b),

(a)ST Microelectronics, Agrate Brianza, (b)University of Cagliari



Historically the aerospace market has always chosen high level reliability solution through custom technology processes application oriented, in order to match the requirement coming from mission profile and harsh environment conditions.

In parallel, Automotive trends have become more and more severe in term of reliability targets. As consequence qualification activity evolved, passing from stress driven approach based only on AEC-Q100 reference specification to a failure mode driven approach oriented to satisfy robustness criteria required by TIER1 and Car Makers.

Aerospace and Automotive worlds have started to converge in terms of reliability approach fundamentals.

Starting from this scenario, new market opportunities for Automotive devices can be identified since the most reliable of them are today eligible to be sold to Aerospace manufacturers with important cost saving thanks to massive production volumes of consolidated technologies.

Obviously a gap may still persist due to the different application purpose and environmental conditions and such gap must be carefully explored.

First of all, a study of the application constraints has to be carried out and once the functional blocks are identified, additional design simulations and supply chain screening have to be implemented in order to guarantee the time-0 functionality & quality.

The potential failure modes activated by cold unbalanced mission profile, atmospheric pressure and radiations have been analyzed; the experimental evidences have been collected as first step on advanced CMOS technologies, while its extension to the world on which digital and power coexist together will be discussed.



Reconsideration of TDDB Reliability of Gate Dielectrics:

Mechanisms and Statistics

Kenji Okada, TowerJazz Panasonic Semiconductor (TPSCo)



Reliability has been recognized as the showstopper of various kinds of state-of-the-art devices.  On the TDDB reliability of gate dielectrics, various characteristics such as the stress voltage dependence and the statistical distribution of intrinsic lifetime (TBD) seems to be successfully explained by the combination of the power-law (PL) model [1] and the percolation model [2]. To deepen the understandings on the mechanisms, we have performed careful reexaminations with gate dielectrics of various thicknesses and have revealed the limitation of these models. As for the TDDB mechanism, we recently reconfirmed the validity of the DCC model [3] we proposed more than 10 year ago and demonstrated the voltage- and thickness-independent defect generation efficiency of hole and of electron against the expectation of the PL model.  The DCC model is consistent with the GSCI model which we proposed for high-k stacked gate dielectrics [4] and provides longer predicted lifetimes at the actual device operating voltages than the PL model. As for the statistical distribution of TBD, it has been revealed that the basic concept of the percolation model, that is, breakdown occurs when a conduction path from cathode to anode is created with generated traps, is valid for limited thickness region [5].  Based on the results, we have proposed a generalized model which is capable to explain whole thickness region. These deeper understandings on the TDDB reliability is expected to realize further advances of not only Si CMOS-based devices but also Si/SiC power devices having gate dielectrics.


[1]   E. Wu et al., “Experimental Evidence of TBD Power-Law for Voltage Dependence,” Trans. on Electron Devices, 49 (2002) 2244.

[2]   R. Degraeve et al., “A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides,” Int. Electron Devices Meeting, (1995) 863.

[3]   K. Okada et al., “A Consistent Model for Time Dependent Dielectric Breakdown in Ultrathin Silicon Dioxides,” Int. Electron Devices Meeting, (1999) 445.

[4]   K. Okada et al., “Model for dielectric breakdown mechanism of HfAlOx/SiO2 stacked gate dielectrics dominated by the generated subordinate carrier injection,” Int. Electron Devices Meeting, (2004) 721.

[5]   K. Okada et al., “Generalized Model of Dielectric Breakdown for Thick and Thin SiO2 and Si3N4 films Combining Percolation Model and Constant-E model,” Int. Reliability Physics Symp., (2017) 5B.2.


Wednesday, September 28th



Technologies of IoT - Challenges and Chances for Fault Isolation

Christian Boit, Technische Universität Berlin, Berlin, Germany



The evolution of electronic devices for Integrated Circuits as we know it through Moore’s law, is one of the fastest industrial development speeds – and still far too slow for the requirements of the age that is described as “Internet of Things” (IoT). ITRS roadmap has been discontinued in 2015. The explosion of data collection, exchange and storage by IoT will require a dramatic increase of operating frequency, requiring very low power, radio frequency, sensors & actuators. All these aspects will have consequences for Contactless Fault Isolation (CFI) that go far beyond the challenges of the past, being mostly imaging resolution and operating frequency with a given basic material of silicon. The presentation will start with an assessment of the CFI innovation in reach, optical probing using visible light, and will expand discussing the influence of new materials for actives, optical interconnects, ultra shallow TSV and more in the aspect of missing external testability on RF level and will give a vision how these challenges may be mastered by taking chances for new concepts of debug and failure analysis.


Thursday, September 29th



A review of Vth instabilities in GaN MISHEMTs

Clemens Ostermaier, Infineon Villach, Germany



Threshold voltage instabilities are one of the major hurdles to establish normally-off III-N MIS-HEMTs. The typical gate stack of such devices consists of a double dielectric layer structure with an insulator on top of the III-N barrier, creating a “remote” interface with a certain distance to the 2DEG channel. Even though this reduces the effect of interfacial charges on the threshold voltage, the III-N/dielectric interface seems currently not stable enough to provide sufficient low drift during operational conditions over lifetime. In this contribution we discuss the minimum stability requirements from an application point of view and suitable measurement techniques to adequately characterize the lifetime conditions. We will discuss different potential defects and physical mechanisms that might be involved into dynamic effects from the buffer, the barrier and the III-N/dielectric interface including the interaction of surface donors with the interface defects.

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