Workshops > Emerging challenges Workshop

“Emerging challenges for a built-in reliability in innovative Automotive ICs“

Moderators: A. Mancaleoni (Package Reliability Principal Engineer - Senior Member of Technical Staff, STMicroelectronics, Agrate Brianza, Italy), Prof. M. Vanzi (Full Professor @ DIEE, University of Cagliari, Italy)

Organizer from STMicroelectronics, Italy: D. Appello (Product Engineering Director - Senior Member of Technical Staff), G. Graziosi (Senior Package Designer - Senior Member of Technical Staff), R. Enrici Vaion (Quality & Reliability Senior Engineer - Automotive Digital Products), M. Medda (Failure Analysis Senior Engineer - Automotive Smart Power Products)


The new automotive applications drive a faster introduction of innovative solutions in silicon design, process and packaging. In front of the new frontiers of integration, from system on chip to system on package, combined with harsh application environment, the effectiveness of stress-driven qualification strategies need to be carefully verified. Reliability mindset should be brought inside the product development cycles since its earliest phases, with growing focus on two complementary aspects:

Main topics will be considered:

  • Physics of failure related to interconnections, with a technology-specific reliability modeling to be developed and applied in tight adherence with the mission profile.
  • New methodologies to design robust interconnections, and consequently to improve the relevant test coverage aimed at screening non-conventional failure modes.

Workshop Structure:3 hours discussion, the work space will be organized in:

  • 2 hours of speeches 3 from STMicroelectronics Italy
    • ST 1st ) Package Interconnection reliability versus harsh Automotive requirements

Case-specific acceleration modelling to extend the scope of stress driven qualification.

  • ST 2nd) Combining high complexity and robust design in Automotive packaging

Extreme miniaturization and integration, connectivity complexity and layout challenges require robust design solutions to reach the excellence in performance. With focus on BGA package, co-design methodology and main design techniques needed to achieve a robust and reliable layout are described. Electrical modeling, fully integrated inside the design flow, demonstrates the effectiveness of proposed solutions.

  • ST 3rd) Reliability, Testability and Testing of High Complexity Package

Efforts toward the extrapolation of faults from experience and technology roadmap to ensure full awareness between testability and testing of defectiveness introduced at back-end manufacturing

Plus 2 from external contributor selected among call for presentation

  • 1 hour dedicated to a final round-table discussion for conclusion

Call for workshop presentations

For the 2 non STMicroelectronics speeches, please send your proposals (before May 31st) to: alberto.mancaleoni@st.com or vanzi@diee.unica.it. Contributions will be very welcome for the round table also

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